Minister Ashwini Vaishnaw announced the India Semiconductor Mission is reducing central capital support for fabrication projects to 40% under Semicon 2.0, down from 50% in the first phase. The shift arrives as three approved fabs—Micron's $2.75B ATMP facility in Gujarat, Tata's $11B partnership with PSMC in Dholera, and CG Power's $2.4B line in Sanand—move toward groundbreaking. Vaishnaw told reporters the adjustment reflects matured state incentive structures and won't dent global interest.
The timing is specific. Phase one committed $10.5B in total subsidies across those three projects, averaging 48% central support when state packages were bundled separately. Under the new structure, the Centre caps at 40%, with states like Gujarat and Maharashtra offering co-investment that reaches 10-15% additional support for greenfield sites. The arithmetic works cleanly for ATMP and legacy-node projects where capex-per-wafer remains manageable. For sub-28nm logic fabs—the segment India publicly targets to compete with Taiwan and Korea—the 10 percentage point reduction translates to $1.5B-$2B in additional private capital requirements for a $15B-$20B leading-edge facility. No chipmaker has announced interest at that scale.
Allocators should note the policy change follows quiet pressure from the Finance Ministry, which flagged subsidy commitments exceeding $18B through 2030 in internal reviews last quarter. The revised cap allows Delhi to market $30B in theoretical semiconductor investment without breaching $12B in direct fiscal exposure. Vaishnaw's public confidence relies on two assumptions: first, that TSMC or Samsung will anchor a sub-10nm project by late 2025, accepting the lower subsidy in exchange for IP protections and talent guarantees India now offers; second, that state governments will stretch co-investment beyond 15% for marquee projects. Neither assumption has been tested. The three approved fabs remain assembly, testing, and mature-node plays—high-volume, lower-margin segments where 40% subsidy still clears IRR hurdles.
The second-order effect is pricing power. Taiwan and South Korea offer 25-30% direct subsidies for leading-edge fabs, but layer opaque utility rebates, land grants, and tax holidays that reach 40-45% effective support. India's transparency—publishing exact subsidy percentages—creates comp pressure other governments avoid. If Semicon 2.0 closes $8B-$12B in new commitments by mid-2026 at the 40% rate, the policy holds. If no sub-28nm anchor emerges by year-end 2025, expect states to announce "special economic frameworks" that quietly restore combined support above 50% without calling it a federal subsidy. The Tata-PSMC project is the test case: 28nm mature logic, $11B capex, 40% central support, Gujarat adding 12%. If returns satisfy PSMC's board, the model works. If Tata renegotiates or delays Phase 2 expansion, the subsidy cut was premature.
Watch three markers through Q2 2025. First, whether TSMC's India delegation—expected in Bengaluru by March—requests a carve-out from the 40% cap for advanced packaging or 7nm pilot lines. Second, CG Power's final investment decision on capacity additions beyond the initial 40,000 wafers per month; that decision reveals whether 52% all-in support (central plus state) clears the margin threshold for power semiconductors. Third, any Finance Ministry guidance on "strategic sector" exceptions that would restore 50% support for defense-critical chips or automotive-grade SiC. Vaishnaw's statement today specifically avoided those verticals.
The policy is a bet that India's $33B electronics production-linked incentive and 1.2M engineering graduates annually matter more than the last 10% of subsidy. The bet assumes chipmakers care more about thirty-year talent pipelines than Year One IRR. TSMC's Arizona experience—$40B committed, $6.6B in federal grants, still losing $200M per quarter on startup costs—suggests otherwise.
The takeaway
India's 10-point subsidy cut tests whether labor access beats capital support for sub-28nm logic. Answer arrives by Q2 2025.
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