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India's **$10 billion** semiconductor incentive program funds four fabs targeting mature nodes, operational by 2026 — execution hinges on talent pipelines and equipment delivery, not capital.
$10.1 billion
in capital commitments and direct government subsidies covering up…
50%
of project costs
$11 billion
joint venture between Tata Electronics and Taiwan's Powerchip Semiconductor…
28-nanometer
and larger nodes with initial capacity of
India's Ministry of Electronics and Information Technology approved four semiconductor fabrication projects in March 2024, backed by $10.1 billion in capital commitments and direct government subsidies covering up to 50% of project costs. The largest facility, a $11 billion joint venture between Tata Electronics and Taiwan's Powerchip Semiconductor Manufacturing Corporation in Dholera, Gujarat, will produce chips on 28-nanometer and larger nodes with initial capacity of 50,000 wafers per month. Construction began in September. First commercial production is scheduled for late 2026.
The incentive framework — India Semiconductor Mission, launched in December 2021 — offers fiscal support calculated at 50% of capital expenditure for display fabs and compound semiconductors, 30% for outsourced semiconductor assembly and test facilities. The program commits INR 760 billion (approximately $9.1 billion) over eight years. New Delhi approved three additional projects in the past eighteen months: CG Power and Industrial Solutions will build a compound semiconductor facility in Sanand, Gujarat; Kaynes Semicon in Sanand and OSAT facility by Tata Electronics in Morigaon, Assam. Combined, the four projects represent $15.2 billion in private and public capital, with 20,000 direct jobs projected by 2028.
This matters because India currently imports 100% of its semiconductor requirements, a $24 billion annual spend growing at 13% compound rate as domestic electronics manufacturing expands. The country produces 3% of global electronics by value but consumes chips at scale — 620 million smartphones shipped domestically in 2023, third-largest automotive market in units, defense electronics modernization requiring indigenous supply. The approved fabs target mature nodes (28nm to 180nm) used in automotive, power management, and industrial applications, not leading-edge logic for AI accelerators or smartphone processors. That positioning avoids direct collision with TSMC and Samsung but addresses the 65% of global chip demand by volume that sits in mature nodes. Geopolitical tailwinds are explicit: Washington views India as hedge against Taiwan risk, Brussels as alternative to Chinese supply chains. The U.S.-India Initiative on Critical and Emerging Technology, announced in January 2023, includes semiconductor supply chain cooperation; the EU committed €90 million in joint research programs through Horizon Europe.
The execution risk is not capital — the subsidy framework is generous and Tata's balance sheet supports multi-year construction timelines. The constraint is talent and operational depth. India graduates 1.5 million engineers annually but fewer than 20,000 have semiconductor-specific training. The Indian Institute of Science in Bangalore and IIT Bombay launched dedicated semiconductor fabrication programs in 2023, but pipeline maturity lags facility commissioning by five years. Tata hired 250 technicians from Taiwan and South Korea for the Dholera project; long-term yield and uptime metrics depend on knowledge transfer velocity. Second risk: input dependencies. India has no domestic equipment supply for lithography, deposition, or etching tools. The fabs will rely on ASML, Applied Materials, Tokyo Electron — same vendors with 18-24 month lead times that bottlenecked global capacity expansion in 2021-2022. New Delhi has not secured priority equipment allocation agreements publicly disclosed.
Allocators should track equipment delivery schedules for the Tata-Powerchip Gujarat facility through Q2 2025 — delays beyond that quarter push first-wafer timelines into 2027 and compress ramp economics. Watch for joint ventures or licensing agreements between Indian firms and Japanese or European chipmakers in analog and power semiconductors, a segment where patent intensity is lower and India's cost structure offers 30-35% labor arbitrage versus existing Southeast Asian fabs. Monitor defense procurement policy — if India's Ministry of Defence mandates indigenous semiconductor content in avionics and communications systems by 2026, that creates captive demand worth $1.2 billion annually and de-risks early-stage fab utilization.
The Dholera facility's equipment installation begins in Q1 2025. That is the line where policy becomes yield curves.
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For the principal
Consider exposure to Indian infrastructure debt or equity co-investment in semiconductor ancillaries — equipment installation and facility management, not fabs directly.
For the operator
Track Tata Electronics Gujarat facility commissioning milestones through mid-2025; delays signal broader India semiconductor execution risk worth 200-basis-point discount on related positions.
For the house
No direct India semiconductor exposure in named accounts; monitoring for secondary plays in testing/assembly and materials supply — decision point Q2 2025 post-equipment delivery.
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