India's semiconductor buildout is entering its second phase. The government's $10 billion incentive program, initially weighted toward chip design startups and foreign fab commitments, is now channeling capital into testing, packaging, and volume manufacturing support. The shift follows a 27-month period in which Indian fabless companies developed custom chips for automotive, defense, and mobile applications but found no domestic path to mass production. Designs went to Taiwan and Malaysia for assembly. That changes this quarter.
Three semiconductor testing and packaging facilities broke ground in Gujarat and Karnataka between November and January, backed by a combined $1.8 billion in public-private capital. Renesas Electronics and Micron Technology are co-anchoring the Gujarat site, targeting 40,000 wafer-equivalent test cycles monthly by Q3 2026. The Karnataka facility, led by Tata Electronics and a consortium that includes Israel's Tower Semiconductor, will handle advanced packaging for chips below 7 nanometers. Both sites are hiring from Taiwan Semiconductor Manufacturing Company's Kaohsiung packaging division, with 183 engineers already relocated under multi-year contracts. India now has visible infrastructure to take a chip from RTL to packaged unit without leaving the subcontinent.
The strategic calculus is straightforward. Indian fabless companies shipped 312 chip designs for tape-out in 2024, up 58% year-over-year, but only 22 of those went into serial production. The remainder stalled at prototype or low-volume runs because clients required local supply assurance that did not exist. Defense contractors, in particular, refused to scale orders for indigenously designed radar and communications chips if final assembly remained in Penang or Hsinchu. The new testing and packaging infrastructure removes that objection. It also positions India to absorb production overflow as U.S. export controls tighten around Chinese assembly of chips designed in third countries. Worth noting: the Karnataka facility has already received inquiries from 11 American fabless companies exploring non-China packaging routes for automotive-grade chips.
Allocators should track three developments over the next 18 months. First, whether Indian packaging yields match Taiwan benchmarks—target is 94% first-pass yield for flip-chip ball-grid arrays by December 2025. Second, the ramp speed of domestic substrate supply, currently India's binding constraint. Substrate production for high-density interconnects is scheduled to begin in Uttar Pradesh in Q4 2025, but the timeline has already slipped once. Third, the Ministry of Electronics and Information Technology is expected to announce a $2.4 billion tranche for fab-scale production incentives in May 2025, likely targeting 28-nanometer and mature nodes. If that capital commits, India will have a continuous semiconductor pathway from IP block to finished module.
The first 5,000 units of an Indian-designed, Indian-packaged automotive microcontroller ship to Mahindra Electric in April 2025.