India formalized Semicon 2.0 on Sunday with a ₹1.27 trillion authorization through fiscal 2030, offering 40% capex support for fabrication facilities and targeting a second commercial silicon fab by 2031. The scheme represents a ₹760 billion increase over the initial India Semiconductor Mission envelope and a 10-percentage-point subsidy reduction that the Ministry of Electronics and IT insists will not deter global chipmakers.
Tata Electronics broke ground on India's first 12-inch wafer fab in Dholera, Gujarat, in March, partnering with Taiwan's Powerchip Semiconductor Manufacturing Corporation under the original 50% subsidy regime. That facility, targeting 28-nanometer nodes and 50,000 wafers per month at maturity, is scheduled for production in 2026. Semicon 2.0 separately supports CG Power's display fabrication plant in Pune, already under construction with 50% support grandfathered from the prior tranche, and opens the window for a second logic fab—likely 65-nanometer or coarser geometries—aimed at automotive, industrial, and defense applications.
The subsidy haircut to 40% reflects two calculations. First, India now has one operational precedent and a 27-month construction timeline from site clearance to tool move-in, reducing perceived execution risk. Second, Delhi is betting that ₹100,000 crore in approved downstream assembly, test, and packaging investments—Micron Technology in Gujarat, CG Power and Kaynes Technology elsewhere—create sufficient demand signal that a second fab sponsor will accept a lower direct subsidy in exchange for guaranteed offtake and tariff protection on imports. Electronics and IT Minister Ashwini Vaishnaw stated flatly that the reduction would not dent appeal, pointing to land acquisition timelines now compressed to 90 days in designated zones and single-window environmental clearances.
Operators and allocators should watch three follow-on events. First, whether a non-Tata sponsor emerges by mid-2026—likely either a Southeast Asian fabless-to-IDM conversion or a trailing-edge foundry seeking a captive India node. Second, whether Semicon 2.0 triggers a compound semiconductor play, since the scheme explicitly covers gallium nitride and silicon carbide with the same 40% subsidy floor; Q4 2025 is the informal deadline for expressions of interest. Third, how China +1 electronics manufacturing shifts interact with the ₹1.7 trillion PLI schemes already committed to smartphones, IT hardware, and telecom—April 2026 is when Ministry of Electronics reviews whether fab capacity matches assembly scale.
India now runs two parallel semiconductor bets: execution risk on Tata-Powerchip at ₹910 billion all-in capex, and scheme risk on whether 40% support proves sufficient to land a second $3–5 billion commitment before the 2031 target window closes.
The takeaway
India cut fab subsidies to 40% but doubled the budget to ₹1.27 trillion, counting on Tata's precedent and downstream pull to land a second plant by 2031.
Editorial & Disclosure Notice: This article was written with artificial intelligence from public sources and is published without individual human review. Artificial intelligence and other digital tools are also used for research, analysis, editing, formatting, and production. Errors, omissions, outdated information, or inaccuracies may occur. References to companies, brands, products, services, organizations, or individuals are for informational and editorial purposes and do not imply endorsement, sponsorship, affiliation, partnership, or approval unless expressly stated. All trademarks and other intellectual property remain the property of their respective owners. Opinions, analysis, estimates, and commentary are informational only and should not be construed as financial, investment, legal, tax, medical, procurement, or other professional advice. Information may be corrected, clarified, or updated after publication. Corrections or removal requests: jenny@pops4.com.
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