India is deploying government incentives approaching $10 billion to establish domestic semiconductor fabrication capacity, positioning itself as a secondary manufacturing pole while Taiwan Semiconductor Manufacturing Company holds 54% of global foundry share. The timing follows Micron's Central New York groundbreaking and persistent institutional flows into TSMC—Cornerstone Investment Partners initiated a position this week—even as allocators acknowledge single-point concentration risk.
The Indian Ministry of Electronics & Information Technology approved three fabrication facilities in Gujarat and Assam over the past eighteen months, offering 50% capital subsidies and ten-year tax holidays. Tata Electronics partnered with Taiwan's Powerchip Semiconductor Manufacturing Corporation for a $11 billion fab in Dholera, targeting legacy nodes at 28nm and above. Tower Semiconductor and Israel's government are backing a second facility. A third project, Kaynes Semicon's assembly plant in Sanand, focuses on packaging rather than wafer fabrication. None compete with TSMC's 3nm leading-edge process, but all address the mature-node shortages that paralyzed automotive and industrial supply chains in 2021.
The strategic calculus resembles the U.S. CHIPS and Science Act's $52.7 billion allocation: pay upfront to diversify away from a Taiwan Strait scenario. TSMC's Arizona fabs will produce 600,000 wafers annually by 2028, still a fraction of Taiwan's 13 million wafer capacity. India's approach targets the same geopolitical insurance premium but at lower capital intensity—legacy nodes require one-tenth the lithography investment of leading-edge. Family offices rotating semiconductor exposure have started asking whether Taiwan-adjacent plays carry embedded tail risk that index weightings ignore. The answer depends on whether you price a cross-strait disruption at 2% or 8% probability over ten years. At 8%, the expected value loss on a TSMC-concentrated portfolio exceeds the carry cost of diversification.
Operators should track yield ramp timelines for Tata's Dholera fab—first wafers are scheduled for Q4 2026—and subsidy disbursement consistency from New Delhi. India's bureaucratic execution risk is non-trivial; the country has announced chip ambitions three times since 2007 without delivering a functioning foundry. This cycle differs because Tata and Powerchip bring operational expertise and because Washington and Brussels are quietly supportive. The U.S. International Development Finance Corporation is evaluating loan guarantees for equipment purchases, effectively underwriting India's build-out as a hedge against Chinese adventurism.
Watch parliamentary budget approvals in July 2025 for the second tranche of semiconductor subsidies. If New Delhi maintains $2 billion annual capital support through 2028, the probability of at least one Indian fab reaching commercial scale exceeds 60%. If funding slips, the projects stall at the equipment procurement stage, and allocators revert to TSMC overweight despite the convexity. The Micron New York facility, breaking ground this month with $100 billion in state and federal support over twenty years, sets the Western subsidy benchmark. India's fiscal commitment will determine whether it joins that club or remains a policy white paper.